H5TQ4G63CFR-RDC  HYNIX(海力士) 集成电路-存储器4Gb DDR3 SDRAM

• VDD=VDDQ=1.5V +/- 0.075V 

• Fully differential clock inputs (CK, CK) operation 

• Differential Data Strobe (DQS, DQS) 

• On chip DLL align DQ, DQS and DQS transition with CK  transition

• DM masks write data-in at the both rising and falling   edges of the data strobe

• All addresses and control inputs except data,  data strobes and data masks latched on the rising edges of the clock

• Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 13  and 14 supported